The present invention relates to voltage-driven self-quenching type semiconductor bidirectional switches as used, e.g., in electric power converters.
FIG. 5 is a cross-sectional view of a prior-art voltage-driven self-quenching type semiconductor bidirectional switch known as "TRIMOS" and described in IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-27, No. 2, pp. 380-387. This device may be interpreted as having a structure that comprises lateral metal-oxide-semiconductor field-effect transistors (MOSFETs) in reverse series connection, and as operating as a bidirectional MOS thyristor. The first p-type well region (p-well region) 31 and the second p-type well region 32 are formed in the upper part of an n-type semiconductor layer (n.sup.- layer) 2. A heavily doped n-type semiconductor region (n.sup.+ region) 41 is formed in the upper part of the p-well region 31. A heavily doped n-type semiconductor region (n.sup.+ region) 42 is formed in the upper part of the p-well region 32. A heavily doped p-type contact region (p.sup.+ -contact region) 51 is formed in the p-well region 31 contacting the n.sup.+ region 41. A heavily doped p-type contact region (p.sup.+ -contact region) 52 is formed in the p-well region 32 contacting the n.sup.+ region 42. An intermediately doped n-type semiconductor region (n region) 12 is formed in the upper central part of the n.sup.- layer 2 between the p-wells 31 and 32. A gate electrode 71 is fixed via an insulation film (gate oxide film) to the portion of the p-well region 31 extending between the n.sup.+ region 41 and the n.sup.- layer 2. A gate electrode 72 is fixed via an insulation film (gate oxide film) to the portion of the p-well region 32 extending between the n.sup.+ region 42 and the n.sup.- layer 2. These gate electrodes 71 and 72 are connected to a common gate terminal G. The first main electrode 81 is fixed to the p.sup.+ - contact region 51. The second main electrode 82 is fixed to the p.sup.+ -contact region 52. The main electrodes 81 and 82 are connected to main terminals T1 and T2, respectively. The n.sup.- layer 2 functions as a drift region of carriers (electrons or holes).
The structure described above may be considered as including lateral MOSFETs in reverse series connection, and also as a bidirectional IGBT or a bidirectional thyristor, as its operation includes a bipolar mode.
When the first main electrode 81 is biased with a negative potential, and the second main electrode 82 with a positive potential, the following conditions arise: An inversion layer is formed in the surface of the p-well region 31 under the gate electrode 81, and electrons are injected from the n.sup.+ region 41 to the n.sup.- layer 2 when a voltage which is positive with respect to the main electrode 81 and higher than the threshold value is applied to the gate terminal G. This inversion layer is usually called "channel". In association with electron injection, holes are injected from the p-well region 32 located on the side of the second main electrode 82. The injected hole current flows in the p-well region 31 to cause a potential drop by the resistance of the p-well region 31. A junction between the p-well region 31 and the n.sup.+ region 41 is biased in the forward direction by the potential drop, causing further electron injection from the n.sup.+ region 41. Thus, the device maintains its ON state without application of a voltage higher than the threshold value to the gate terminal G, and it operates in the thyristor mode. Since the main electrodes T1 and T2 are arranged mutually symmetrical, the device also can be used as a bidirectional switch.
FIG. 6 is a cross-sectional view of a prior-art unidirectional high withstand voltage switch. As shown in FIG. 6, this device has a so-called reach-through type structure that comprises regions corresponding to the n region 12 of FIG. 5, which surround the p-well region to shorten the n.sup.- layer 2.
Again with reference to FIG. 5, if one wants to realize a high withstand voltage in the device, it is necessary to provide the n.sup.- layer 2 with high resistivity. However, when the n.sup.- layer 2 has high resistivity, a depletion layer edge 13 advances beyond the n region 12 meant to function as a stopper of the depletion layer. The advancing depletion layer edge 13 reaches the p-well region 32 on the high potential side to cause the so-called punch-through phenomenon. Thus, the device can no longer maintain its blocking state. If the n.sup.- layer 2 is elongated to overcome the above-described problem, the drift path of the charged particles is also elongated, increasing the on-voltage of the device.
To reduce the on-voltage of devices which operate in the bipolar mode, these are usually designed to have reach-through type structure as shown in FIG. 6. With the n region 12 functioning as a depletion layer stopper, the punch-through phenomenon is prevented while the n.sup.- layer 2 is shortened. However, the n region 12 disposed around the p-well region 32 increases the gate threshold value. Since an abnormally high voltage has to be applied to the gate electrode to turn on the device, the structure of FIG. 6 is not practical for bipolar switches.
Since the gate electrodes 71 and 72 are connected in common, the potential difference between the other main electrode T2 and the gate electrode 82 is increased, causing breakdown of the gate oxide film when the gate electrode is biased with respect to the main electrode T1 on the reference potential side. Thus, the prior-art devices are not suitable for high withstand voltage applications, and their application is limited to an intermediate withstand voltage range.